1. Field of the Invention
The present invention relates to a semiconductor memory test apparatus, and in particular to an improved semiconductor memory test apparatus which is capable of testing a signal margin of a semiconductor memory.
2. Description of the Background Art
FIG. 1 is a view illustrating the internal construction of a known DRAM. As shown therein, there are provided a row control block 1 for generating an internal control signal used for a word line driving operation when a row address strobe bar signal (/RAS) is inputted, a row decoder 2 for decoding an address signal inputted in accordance with a control signal from the row control block 1, a WLMODEL signal generation unit 3 for outputting a word line model signal (hereinafter called "WLMODEL") after a predetermined delay in accordance with a control signal from the row control block 1 and an output signal from the row decoder 2 for corresponding with an actual timing of a word line signal, an amplifier driving signal generation unit 9 for receiving the WLMODEL signal and an output signal from the row decoder 2 and generating a signal for driving a sense amplifier, a CAPEN signal generation unit 10 for receiving a control signal from the row control block 1 and the WLMODEL signal and generating a column address pulse enable (hereinafter called "CAPEN") signal, a Y-address buffer 4 for latching the address signal inputted, an ATD pulse generation unit 5 for receiving an output signal from the Y-address buffer 4 and the CAPEN signal and generating an address transition detection (hereinafter called "ATD") pulse, a PYCb signal generation unit for receiving the ATD pulse and generating a delayed signal pulse Y control bar (hereinafter called "PYCb") signal, a Y-address predecoder 6 for receiving an address signal from the Y-address buffer 4 and decoding the same, a YSEL signal generation unit 11 for generating a Y-SELection (hereinafter called "YSEL") signal in accordance with an output signal from the Y-address predecoder 6, and a sense amplifier 8 for amplifying the data of a corresponding word line in accordance with an amplifier driving signal from the amplifier driving signal generation unit 9 and outputting the data of a corresponding bit line in accordance with the YSEL signal.
FIGS. 2A through 2I are waveform diagrams of an output signal of FIG. 1. The operational timing of the known DRAM will be explained.
First, the /RAS signal becomes active "Low(L)" as shown in FIG. 2A, and the row control block 1 generates an internal control signal used for driving the row decoder 2 and the word line.
The row decoder 2 decodes an X-address signal in accordance with the control signal. When the decoded signal and the control signal from the row control block 1 are inputted into the WLMODEL signal generation unit 3, a WLMODEL signal, shown in FIG. 2B, is generated after a predetermined delay time.
In addition, the WLMODEL signal and the output signal from the row decoder 2 are inputted into the amplifier driving signal generation unit 9 consisting of a NAND-gate and multiple inverter gates, and the amplifier driving signal generation unit 9 generates a sense amplifier enable (SAEN) signal, a sense amplifier down (SN) signal, and an amplifier up bar (SPb) signal, which are shown in FIGS. 2C, 2D and 2E, and then the sense amplifier 8 is driven. The data of all memory cells of the driven word line are amplified by the sense amplifier and are stored into the memory cell and become a ready state until the YSEL signal is applied thereto.
The inputted address signal is inputted through the Y-address buffer 4 and is decoded by the Y-address predecoder 6. The CAPEN signal generation unit 10 which receives the WLMODEL signal and a control signal from the row control block 1 generates a CAPEN signal as shown in FIG. 2F.
In addition, the Y-address signal inputted through the Y-address buffer 4 and the CAPEN signal are applied to the ATD pulse generation unit 5, and an ATD pulse as shown in FIG. 2G is generated. The delay signal PYCb, shown in FIG. 2H, of the ATD pulse is generated by the PYCb signal generation unit 7.
The PYCb signal and the output signal from the Y-address predecoder 6 are applied to the YSEL signal generation unit 11, and a corresponding bit line is selected. The YSEL signal, shown in FIG. 2I, is outputted. The YSEL signal is applied to the sense amplifier 8, and the data of a corresponding line is outputted.
However, in the WLMODEL signal generation unit and the ATD pulse generation unit of the known semiconductor memory, there are provided a delay circuit consisting of CMOS gates and a load device such as a resistant capacitor, so that the timing is adjusted by a circuit simulation.
Therefore, in the known art, the operational timing of a circuit is adjusted by adjusting only a metal mask for implementing a predetermined timing operation based on a process condition and a device characteristic variation when fabricating the product. Therefore, it requires much time for securing an optimum timing. In addition, it is impossible to obtain an accurate modelling.